Advancement in the electronics industry, e.g., personal computers (PC), mobile phones, and personal data assistants (PDA), triggers a need for light, compact, and multi-functional power systems that are capable of processing a lot of data at a time. This need also causes a reduction in the size of semiconductor packages according to the size of a semiconductor chip, i.e., wafer-level chip size package (WLCSP).
In general, in order to fabricate the WLCSP, a wafer can be packaged by a photolithography process and a sputtering process right after the wafer is processed. This method is much easier than a general wafer level packaging process during which dye bonding, wire bonding, and molding are carried out. Further, using the WLCSP, it is possible to make solder bumps for all chips formed on a wafer at a time. In addition, a wafer-level test on the operations of each chip is possible during the WLSCP method. For these and other reasons, a WLCSP can be fabricated at a lower cost than general packaging for semiconductor devices.
FIGS. 1 through 3 are cross-sectional views of conventional wafer-level chip scale packages. Referring to FIG. 1, chip pads 40 are formed of a metal material such as aluminum on a silicon substrate 5. A passivation layer 10 is formed to expose a portion of each of the chip pads 40 on the silicon substrate 5, thereby protecting the silicon substrate 5. A first insulating layer 15 is formed to cover the passivation layers 10, and then a re-distribution line (RDL) pattern 20 is formed on portions of the first insulating layer 15 and the exposed chip pads 40. A second insulating layer 25 is formed on the RDL pattern 20 while exposing portions of the RDL pattern 20. Under bump metals (UBM) 30 are formed between solder bumps 35 and the exposed portions of the RDL pattern 20.
The RDL pattern 20 includes inclined portions when re-distributed on the first insulating layer 15 from the chip pads 40. Thus, short circuits may occur when forming the RDL pattern 20, or the RDL pattern 20 may be cracked due to stresses. Referring to FIG. 2, in a conventional wafer-level chip scale package 50, a RDL pattern 54 adheres to a solder connection 52 in the form of a cylindrical band. Therefore, a contact area between the RDL pattern 54 and the solder connection 52 is reduced, thereby deteriorating the electrical characteristics therebetween. Further, short circuits may occur due to stresses in a contact surface between the RDL pattern 54 and the solder connection 52. Also, the solder connection 52, which is connected with a solder bump 58 formed on a chip pad 56, is exposed to the outside of the wafer-level chip scale package 50, i.e., to air. Thus, there is a higher possibility that moisture penetrates into the solder connection 52, which would lower the reliability of the solder connection 52. In addition, the wafer-level chip scale package 50 is completed by carrying out several processes, and therefore manufacturing costs are increased.
Referring to FIG. 3, in a conventional wafer-level chip scale package 60, a RDL pattern 76 is electrically connected with a chip pad 72 via a connection bump 74. The RDL pattern 76 is, however, inclined on the connection bump 74, thereby causing cracks therein due to stresses. Also, the connection bump 74 is made by performing a plating process, thereby being formed of aluminum, copper, silver, or an alloy thereof. Accordingly, the conventional wafer-level chip scale package 60 is not easy to manufacture.